SetActiveLib -work
comp -include "$dsn\src\misc.vhd" 
comp -include "$dsn\src\constants.vhd" 
comp -include "$dsn\src\control_unit.vhd" 
comp -include "$dsn\src\alu.vhd" 
comp -include "$dsn\src\regbank.vhd" 
comp -include "$dsn\src\cpu.vhd" 
comp -include "$dsn\src\cpu_TB.vhd" 
asim +access +r TESTBENCH_FOR_cpu 
wave 
wave -noreg clock
wave -noreg reset
wave -noreg imemAddr
wave -noreg imemData
wave -noreg dmemAddrRead
wave -noreg dmemAddrWrite
wave -noreg dmemWrEna
wave -noreg dmemDataRead
wave -noreg dmemDataWrite
wave -noreg dmemDataOut
wave -noreg pipeStop
# The following lines can be used for timing simulation
# acom <backannotated_vhdl_file_name>
# comp -include "$dsn\src\cpu_TB_tim_cfg.vhd" 
# asim +access +r TIMING_FOR_cpu 
